#include "24l01.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_spi.h"
#include "ssd1306.h"
#include "spi.h"
const uint8_t TX_ADDRESS0[TX_ADR_WIDTH] = { 0x34, 0x43, 0x10, 0x10, 0x01 };
const uint8_t TX_ADDRESS1[RX_ADR_WIDTH] = { 0x01, 0x58, 0x58, 0x58, 0x58 };
const uint8_t TX_ADDRESS2[RX_ADR_WIDTH] = { 0x02, 0x58, 0x58, 0x58, 0x58 };
const uint8_t TX_ADDRESS3[RX_ADR_WIDTH] = { 0x03, 0x58, 0x58, 0x58, 0x58 };
const uint8_t TX_ADDRESS4[RX_ADR_WIDTH] = { 0x04, 0x58, 0x58, 0x58, 0x58 };
const uint8_t TX_ADDRESS5[RX_ADR_WIDTH] = { 0x05, 0x58, 0x58, 0x58, 0x58 };
const uint8_t RX_ADDRESS0[RX_ADR_WIDTH] = { 0x34, 0x43, 0x10, 0x10, 0x01 };
const uint8_t RX_ADDRESS1[RX_ADR_WIDTH] = { 0x01, 0x58, 0x58, 0x58, 0x58 };
const uint8_t RX_ADDRESS2[1] = { 0x02 };
const uint8_t RX_ADDRESS3[1] = { 0x03 };
const uint8_t RX_ADDRESS4[1] = { 0x04 };
const uint8_t RX_ADDRESS5[1] = { 0X05 };
void NRF24L01_Init(void)
{
	GPIO_InitTypeDef GPIO_InitStructure;
	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC, ENABLE);
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
	GPIO_Init(GPIOA, &GPIO_InitStructure);
	GPIO_SetBits(GPIOA, GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4);
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
	GPIO_Init(GPIOC, &GPIO_InitStructure);
	GPIO_SetBits(GPIOC, GPIO_Pin_4);
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
	GPIO_Init(GPIOC, &GPIO_InitStructure);
	SPI1_Init();
	Clr_NRF24L01_CE;
	Set_NRF24L01_CSN;
	SPI1_SetSpeed(SPI_BaudRatePrescaler_8);
	NRF24L01_Check();
}
uint8_t NRF24L01_Check(void)
{
	uint8_t buf[5] = { 0XA5,0XA5,0XA5,0XA5,0XA5 };
	uint8_t i;
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + TX_ADDR, buf, 5);
	NRF24L01_Read_Buf(TX_ADDR, buf, 5);
	for (i = 0; i < 5; i++)if (buf[i] != 0XA5)break;
	if (i != 5)
	{
		OLED_P6x8Str(0, 0, "24L01 Check Failed!");
		Delay_ms(500);
		return 1;
	}
	else
	{
		OLED_P6x8Str(0, 0, "24L01 Ready!");
		return 0;
	}
}
uint8_t NRF24L01_Write_Reg(uint8_t reg, uint8_t value)
{
	uint8_t status;
	Clr_NRF24L01_CSN;
	status = SPI1_ReadWriteByte(reg);
	SPI1_ReadWriteByte(value);
	Set_NRF24L01_CSN;
	return(status);
}
uint8_t NRF24L01_Read_Reg(uint8_t reg)
{
	uint8_t reg_val;
	Clr_NRF24L01_CSN;
	reg_val = SPI1_ReadWriteByte(reg);
	Set_NRF24L01_CSN;
	return(reg_val);
}
uint8_t NRF24L01_Read_Buf(uint8_t reg, uint8_t *pBuf, uint8_t len)
{
	uint8_t status, uint8_t_ctr;
	Clr_NRF24L01_CSN;
	status = SPI1_ReadWriteByte(reg);
	for (uint8_t_ctr = 0; uint8_t_ctr < len; uint8_t_ctr++)pBuf[uint8_t_ctr] = SPI1_ReadWriteByte(0XFF);
	return status;
}
uint8_t NRF24L01_Write_Buf(uint8_t reg, uint8_t *pBuf, uint8_t len)
{
	uint8_t status, uint8_t_ctr;
	Clr_NRF24L01_CSN;
	status = SPI1_ReadWriteByte(reg);
	for (uint8_t_ctr = 0; uint8_t_ctr < len; uint8_t_ctr++)SPI1_ReadWriteByte(*pBuf++);
	Set_NRF24L01_CSN;
	return status;
}
uint8_t NRF24L01_TxPacket(uint8_t *txbuf)
{
	uint8_t sta;
	Clr_NRF24L01_CE;
	NRF24L01_Write_Buf(NRF24L01_WR_TX_PLOAD, txbuf, TX_PLOAD_WIDTH);
	while (NRF24L01_IRQ != 0);
	sta = NRF24L01_Read_Reg(STATUS);

	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + STATUS, sta);
	if (sta&MAX_TX)
	{
		NRF24L01_Write_Reg(NRF24L01_FLUSH_TX, 0xff);
		return MAX_TX;
	}
	if (sta&TX_OK)
	{
		return TX_OK;
	}
	return 0xff;
}
uint8_t NRF24L01_RxPacket(uint8_t *rxbuf)
{
	uint8_t sta;
	SPI1_SetSpeed(SPI_BaudRatePrescaler_8);
	sta = NRF24L01_Read_Reg(STATUS);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + STATUS, sta);
	if (sta&RX_OK)
	{
		NRF24L01_Read_Buf(NRF24L01_RD_RX_PLOAD, rxbuf, RX_PLOAD_WIDTH);
		NRF24L01_Write_Reg(NRF24L01_FLUSH_RX, 0xff);
		return 0;
	}
	return 1;
}
void RX_Mode(void)
{
	Clr_NRF24L01_CE;
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P0, (uint8_t*)RX_ADDRESS0, RX_ADR_WIDTH);
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P1, (uint8_t*)RX_ADDRESS1, RX_ADR_WIDTH);
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P2, (uint8_t*)RX_ADDRESS2, 1);
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P3, (uint8_t*)RX_ADDRESS3, 1);
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P4, (uint8_t*)RX_ADDRESS4, 1);
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P5, (uint8_t*)RX_ADDRESS5, 1);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + EN_AA, 0x3f);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + EN_RXADDR, 0x3f);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RF_CH, 40);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RX_PW_P1, RX_PLOAD_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RX_PW_P2, RX_PLOAD_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RX_PW_P3, RX_PLOAD_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RX_PW_P4, RX_PLOAD_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RX_PW_P5, RX_PLOAD_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RF_SETUP, 0x0F);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + CONFIG, 0x0f);
	Set_NRF24L01_CE;
	OLED_P6x8Str(0, 1, "RX_Mode");
}
void TX_Mode(void)
{
	Clr_NRF24L01_CE;
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + TX_ADDR, (uint8_t*)TX_ADDRESS0, TX_ADR_WIDTH);
	NRF24L01_Write_Buf(NRF24L01_WRITE_REG + RX_ADDR_P0, (uint8_t*)TX_ADDRESS0, RX_ADR_WIDTH);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + EN_AA, 0x01);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + EN_RXADDR, 0x01);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + SETUP_RETR, 0x1a);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RF_CH, 40);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + RF_SETUP, 0x0F);
	NRF24L01_Write_Reg(NRF24L01_WRITE_REG + CONFIG, 0x0e);
	Set_NRF24L01_CE;
	OLED_P6x8Str(0, 1, "TX_Mode");
}
